NCA-GENL Software Development Practice Question
A team is serving a 70B-parameter LLM with TensorRT-LLM on a node with four GPUs. During load testing they observe that increasing concurrent requests improves throughput up to a point, then latency spikes sharply and GPU memory utilization sits near the limit. Profiling shows the KV cache is being paged out and recomputed. Which change most directly addresses this bottleneck?
⚠ Common exam trap
The trap here is treating a throughput plateau as a batching problem when the profiler shows cache eviction and recomputation.
Answer choices
Why each option matters
Answer the question above first, then reveal the full breakdown to understand why each option is right or wrong.
Correct answer & explanation
✓
Reduce the maximum sequence length and configure a KV cache size that fits in remaining GPU memory, potentially with quantized cache.
Sharp latency growth with memory near the limit and profiler evidence of KV cache paging and recomputation means the cache working set no longer fits. Capping maximum sequence length and explicitly sizing the KV cache, optionally with quantized cache, keeps the cache resident and eliminates recomputation. In-flight batching remains useful, but it must operate within a cache budget that the deployment actually fits.
Answer analysis
Option-by-option breakdown
For each option: why learners choose it and why it is or isn't the right answer here.
- ✗
Enable in-flight batching and increase the maximum batch size so more requests share each forward pass.
Why it's wrong here
In-flight batching already improves GPU utilization by mixing prefill and decode work, but raising the maximum batch size further increases simultaneous KV cache demand. With memory already near the limit, larger batches accelerate paging and recomputation rather than relieving them. The profiler evidence points to cache capacity, not scheduling, so this change worsens the observed symptom.
- ✗
Switch the deployment from tensor parallelism across four GPUs to pipeline parallelism to reduce per-GPU memory pressure.
Why it's wrong here
Pipeline parallelism splits layers across GPUs but each GPU still stores KV cache for the layers it owns, and it introduces pipeline bubbles that hurt latency. It does not reduce the total KV cache footprint for a given concurrency level. The observed paging stems from cache capacity per device, so changing the parallelism strategy alone does not resolve the memory shortfall.
- ✓
Reduce the maximum sequence length and configure a KV cache size that fits in remaining GPU memory, potentially with quantized cache.
Why this is correct
The paging and recomputation indicate that the KV cache exceeds available memory as concurrency rises. Capping maximum sequence length and sizing the cache explicitly, optionally with FP8 or INT8 KV cache quantization, keeps the working set resident and removes the recompute penalty. This directly targets the profiled bottleneck while preserving the existing four-GPU tensor-parallel layout.
- ✗
Increase the tensor-parallel degree beyond four GPUs so the model weights and cache are spread across more devices.
Why it's wrong here
The node has only four GPUs, so raising tensor parallelism past that count is not physically possible without adding hardware. Even with more GPUs, tensor parallelism adds all-reduce communication overhead. The question asks for the most direct fix to cache paging on the existing node, which is right-sizing the cache and sequence length rather than scaling out devices.
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JA
Written and reviewed by Johnson Ajibi, MSc IT Security
Senior Network & Security Engineer · founder of Courseiva
Last reviewed September 2026 · checked against the official NVIDIA exam blueprint
This NCA-GENL practice question is part of Courseiva's free NVIDIA certification practice question bank. Courseiva provides original exam-style practice questions with explanations, topic-based practice, mock exams, readiness tracking, and study analytics to help learners prepare for the NCA-GENL exam.