CISSP Security Architecture and Engineering Practice Question
This CISSP practice question tests your understanding of security architecture and engineering. The scenario asks you to isolate a root cause — eliminate options that address a different problem before choosing. After answering, compare your reasoning against the explanation and wrong-answer breakdown below. Once you have made your selection, read the full explanation to reinforce the concept and understand why each distractor is designed to mislead on exam day.
A security architect is reviewing a system that uses a microkernel operating system. The architect is concerned about potential side-channel attacks between processes. Which mitigation is most effective at the architecture level?
Answer the question above first, then reveal the full breakdown to understand why each option is right or wrong.
Correct answer & explanation
✓
Use cache partitioning or cache coloring to isolate process caches
D is correct because cache partitioning or cache coloring directly addresses the root cause of side-channel attacks in a microkernel environment: shared CPU caches. By isolating each process's cache footprint, an attacker cannot infer sensitive data (e.g., cryptographic keys) through timing variations or cache occupancy measurements, which is a fundamental architectural mitigation.
Key principle: Answer the scenario, not the keyword: identify the specific constraint before choosing the most familiar-sounding option.
Answer analysis
Option-by-option breakdown
For each option: why learners choose it and why it is or isn't the right answer here.
✗
Randomize the address space layout (ASLR)
Why it's wrong here
ASLR protects against memory corruption, not side channels.
✗
Implement stack canaries in all user-space applications
Why it's wrong here
Stack canaries detect buffer overflows, not side channels.
✗
Reduce the number of system calls and IPC mechanisms
Why it's wrong here
Microkernels already have minimal IPC; reduction does not address side channels.
✓
Use cache partitioning or cache coloring to isolate process caches
Read the scenario before looking for a memorised answer.
Common exam traps
Common exam trap: answer the scenario, not the keyword
The trap here is that candidates often confuse software-based mitigations (ASLR, stack canaries) with hardware-level side-channel defenses, or mistakenly think reducing IPC eliminates all covert channels when the real threat is shared microarchitectural state.
Detailed technical explanation
How to think about this question
Cache coloring works by mapping physical memory addresses to specific cache sets so that processes with different colors never occupy the same cache lines, preventing cross-process cache eviction and timing analysis. In a microkernel, where most services run in user space, shared L2/L3 caches become a prime covert channel; hardware-enforced cache partitioning (e.g., Intel Cache Allocation Technology) can assign exclusive cache ways to critical processes. Real-world attacks like Prime+Probe or Flush+Reload rely on shared cache state, making this mitigation essential for high-assurance systems.
KKey Concepts to Remember
Read the scenario before looking for a memorised answer.
Find the constraint that changes the correct option.
Eliminate answers that are true in general but not in this case.
TExam Day Tips
→Watch for words such as best, first, most likely and least administrative effort.
→Review why wrong options are wrong, not only why the correct option is correct.
Key takeaway
Answer the scenario, not the keyword: identify the specific constraint before choosing the most familiar-sounding option.
Real-world example
How this comes up in practice
A developer is choosing between AES-256 (symmetric) and RSA-2048 (asymmetric) for encrypting a large file that will be sent to a partner. Symmetric encryption is fast but requires key exchange; asymmetric is slower but solves the key distribution problem. A hybrid approach — encrypt the file with AES, encrypt the AES key with RSA — is standard. Questions like this test whether you understand when each approach applies.
Related glossary terms
Concepts from this question explained
These glossary pages explain the core terms tested in this CISSP question in full detail.
Security Architecture and Engineering — This question tests Security Architecture and Engineering — Read the scenario before looking for a memorised answer..
What is the correct answer to this question?
The correct answer is: Use cache partitioning or cache coloring to isolate process caches — D is correct because cache partitioning or cache coloring directly addresses the root cause of side-channel attacks in a microkernel environment: shared CPU caches. By isolating each process's cache footprint, an attacker cannot infer sensitive data (e.g., cryptographic keys) through timing variations or cache occupancy measurements, which is a fundamental architectural mitigation.
What should I do if I get this CISSP question wrong?
Identify which exam domain this question belongs to, review the core concept, then practise similar questions from the same domain.
What is the key concept behind this question?
Read the scenario before looking for a memorised answer.
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Question Discussion
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